1. Field of the Invention
The present invention generally relates to solid state image sensing elements and, more particularly, is directed to a CCD (charge coupled device) image sensor of an interline transfer system and a CCD image sensor of a frame interline transfer system.
2. Description of the Prior Art
Transfer electrodes in a vertical register of a conventional CCD solids state imager, for example, are wired such that lead wire units extending in the horizontal direction and electrode units projecting along the vertical register are formed as one unit by a polycrystalline silicon layer, for example.
A CCD solid state imager of a full-pixel read out system having transfer electrodes of three layers to which three-phase drive pulses having different phases are supplied will be described more fully. As shown in FIGS. 1 and 2, a transfer electrode 21 formed of a first polycrystalline silicon layer comprises s first leader 21a extending in a light sensing portion 26 (region shown by a width Ws in FIG. 2) and a first electrode portion 21b (shown by a solid line in FIG. 2) downwardly projecting along a vertical register 27 (region shown by a width Wr in FIG. 2). A transfer electrode 22 formed of a second polycrystalline silicon layer comprises a second leader 22a extending in the horizontal direction on the first leader 21a and a second electrode portion 22b (see a solid line in FIG. 2) upwardly projecting along a vertical register 27. A transfer electrode 23 formed of a third polycrystalline silicon layer comprises a third leader 23a extending in the horizontal direction on the second leader 22a and a third electrode portion 23b (see a one-dot chain line in FIG. 2) downwardly projecting from the end portion of the second electrode portion 22b along the vertical register 27. In FIG. 2, a region shown by a width Wc represents a channel-stopper region.
In the above conventional CCD solid state imager, the first, second and third leader portions 21a, 22a, and 23a in the respective transfer electrodes 21, 22 and 23 are wired on the space between the light sensing portions in the vertical direction. Further, when the respective transfer electrodes 21, 22 and 23 are formed by the patterning-process, misalignment must be taken into consideration. Therefore, the wiring widths of the leader portions 21a, 22a and 23a must be decreased in the upper layers. That is, assuming that W.sub.1, W.sub.2, and W.sub.3 represent wiring widths in the first, second and third leader portions 21a, 22a and 23a, then a relationship of W.sub.1 &gt;W.sub.2 &gt;W.sub.3 must be established.
Since the wiring width W.sub.3 in the third leader portion 23 is reduced the most as described above, the wiring resistance in the third leader portion 23a is increased, which causes a propagation delay of a drive pulse. The propagation delay of the drive pulse causes a failure in electric charges processed by the vertical register 27 and a failure in the transfer of electrical charges. There is then the disadvantage that the picture quality is considerably deteriorated. In particular, when the drive pulses are supplied from the left and right ends of the respective transfer electrodes 21, 22 and 23, a propagation delay of drive pulse occurs in the central portion of the image region. Consequently, there are disadvantages in that an electrical charge failure and a failure of electrical charge transfer may occur in the central portion.
Therefore, it is proposed that the wiring width W.sub.3 of the third leader portion 23a be increased. In this case, the wiring width W.sub.1 of the first leader portion 21a is increased and the opening width of the light sensing unit 26 is decreased. There is then the disadvantage that the sensitivity decreases. Further, it is proposed that the wiring widths W.sub.2 and W.sub.3 of the second and third leader portions 22a and 23a be made the same. It is, however, very difficult to form the wiring widths W.sub.2 and W.sub.3 the same because of misalignment or the like in the patterning-process.
As another method, there is proposed a method in which the respective transfer electrodes 21, 22 and 23 are formed of polycrystalline silicon layers and tungsten silicide layers, i.e., formed as a polycide structure. In this case, as compared with the case where the transfer electrode is formed of only the polycrystalline silicon layer, there is the advantage that the wiring resistance can be considerably reduced.
When the CCD imager is applied to the image sensor of a frame interline transfer system, an electrical charge transfer speed of 40 to 100 times the transfer speed of the interline transfer system image sensor is required. Therefore, only by making the transfer electrode low in resistance can the aforesaid disadvantages be removed. In addition, the aforesaid method cannot be at present be accomplished to the extent such that the characteristics will not be deteriorated. Accordingly, a new process must be developed.
To solve the problems, there is proposed a technique in which the third transfer electrode is shunted by a metal film such as Al or the like. In the transfer electrode pattern of FIG. 2, the first electrode portion 21b in the first layer is covered with the third electrode portion 23b in the third transfer electrode 23 so that a shunt structure in which the metal films are connected to the transfer electrodes 21, 22 and 23 of the respective layers cannot be realized.
Therefore, there is proposed a method in which the third transfer electrode 23 is formed across the light sensing portion 21 in the horizontal direction to thereby expose the electrode portions 21b, 22b and 23b of the respective transfer electrodes 21, 22 and 23. In this case, metal films 31 formed along the vertical register on the respective transfer electrodes 21, 22 and 23 and the respective transfer electrodes 21, 22 and 23 can be easily electrically connected, thereby making it possible to easily make a shunt structure. In the illustrated example, with respect to (3n+1)'th column (n=0, 1, 2 . . . ), the third transfer electrode (third electrode portion 23b) and the metal film 31 are connected. With respect to the (3n+2)'th column, the first transfer electrode (first electrode portion 21b) and the metal film 31 are connected. Then, with respect to the (3n+3)'th column, the second transfer electrode (second electrode portion 22b) and the metal film 31 are connected.
In the CCD solid state imager shown in FIG. 3, since the third transfer electrode 23, particularly, the third leader portion 23a crosses the light sensing portion 26, an effective opening ratio of the light sensing portion 26 is decreased and the influence of noise of a signal charge during a low intensity illumination (shot noise) is increased. Also, depending on the voltage condition of the drive pulse supplied thereto, the surface of the light sensing portion 26 becomes a depletion layer and the dark current is increased.
In other proposed examples, as shown in FIGS. 4 to 7, the first electrode portion 21b in the first transfer electrode 21 projects downwardly along the vertical register (see FIG. 5) and the second electrode portion 22b in the second transfer electrode 22 is projects upwardly along the vertical register (see FIG. 6). The third electrode layer 23 comprises as shown in FIG. 7 a short-circuit electrode portion 23S which extends in the vertical transfer direction in a certain column, a first electrode portion 23b.sub.1 which projects downwardly along the vertical register in another column and a second electrode portion 23b.sub.2 which projects upwardly along the vertical register in another column.
As shown in FIG. 4, since the respective transfer electrodes 21, 22 and 23 are sequentially laminated, the light sensing portion 26 is not crossed by the third transfer electrode 23 and the electrode portions 21b, 22b, 23b.sub.1 and 23b.sub.2 of the respective transfer electrodes 21, 22 and 23 can be exposed, thereby realizing the full-pixel read out CCD image sensor of the frame interline transfer system without deteriorating the characteristics.
Further, in the CCD solid state image sensor shown in FIG. 4, the full pixel read out type is generally adopted. There is then the advantage that, a signal processing circuit of the succeeding stage can be simplified in the image processing of a non-interlace system.
When the CCD solid state image sensor having the transfer electrodes 21, 22 and 23 of the three layers is applied to the interlace system image processing such as an NTSC system or the like, the field read out system and the frame read out system are required for a signal charge read out system. According to the above CCD solid state image sensor, when signal charges of the light sensing portion 26 are read out under the first transfer electrode 21 or under the second transfer electrode 22, the read out system can be made so as to correspond to the field read out system or the frame read out system. However, when signal charges from the light sensing portion 26 are read out under the third transfer electrode 23, the field read out system and the frame read out system become impossible.
In actual practice, it is preferred that electrical charges are read out from the electrode of third layer. Because the electrode of third layer is opposed to the center of the light sensing portion and therefore, an electric field for read-out is easily applied to the whole of the light sensing portion. Also, when signal charges are read out by this electrode of the third layer, the opening portion from the light sensing portion to the channel is widest. The present invention will be described hereinafter on the assumption that signal charges are read out by the electrode of the third layer.
Further, when electrical charges are read out, a read out potential is applied to the read-out electrodes at the same time. At that time, the following problems occur. That is, a substrate potential is fluctuated by the potential applied to the electrode and the read-out operation becomes difficult or a higher potential is required in the read-out operation. Accordingly, it is desired that the read-out operation be carried out in every row at different timings.
Furthermore, it is preferred that the electrode area be made as small as possible. The reason for this is to reduce the influence exerted upon the substrate potential.
In the CCD solid state image sensor shown in FIG. 4, the third transfer electrode is supplied with only the same drive pulse on the short-circuit electrode portion 23S. Therefore, the above pulse driving method cannot be realized.